Embodiments of the invention relate generally to electronics packages and, more particularly, to stackable electronics packages for stacking solid-state switching devices in a modular fashion and with low inductance.
Wide-bandgap semiconductor devices are expected to be widely adopted for power switches as production costs are reduced, with Gallium Nitride (GaN) and silicon carbide (SiC) transistors being prime examples of such devices. These devices offer low on-resistance and high current capability per unit active area of the device and provide the capability for high speed switching, high band width, and high-power density. However, it is known that wide-bandgap semiconductor devices are highly sensitive to packaging layout, as the proximity of circuitry in the packaging—as well as additional gate driver, bus capacitors, and power connectors in the packaging—affects the performance of the devices due to parasitic impedance. Even good standard packaging concepts can add several nH of inductance to a device commutation loop, but for the speed of most wide-bandgap semiconductor devices, the total commutation loop needs to be below 1 nH to achieve device level performance.
Additionally, the high current capability of wide-bandgap semiconductor devices means that such devices often carry high current densities. This carrying of high current densities makes wide-bandgap semiconductor devices less compatible with traditional PCB style design rules, as the copper thickness and via dimensions usually suitable for high frequency designs are not well suited for high current operation. The ability to package a single device is one hurdle based on the above identified issues, but packaging becomes more of a challenge when design requirements call for packaging of multiple devices, such as in a half-bridge arrangement or the arrangement of several devices in parallel to achieve the required current.
Accordingly, it would be desirable to provide a low inductance electronics package for wide-bandgap semiconductor devices that can reduce the overall commutation loop to less than 1 nH, and preferably less than 0.5 nH, for a half-bridge configuration, without additional electromagnetic interference or localized bus capacitance. It would also be desirable for the electronics package design to support the integration of many devices and to provide a low profile that allows for integration of the package into space constrained areas and devices, such as wheel wells or motor housings.